Notice Board :

Call for Paper
Vol. 5 Issue 10

Submission Start Date:
Oct 01, 2018

Acceptence Notification Start:
Oct 10, 2018

Submission End:
Oct 15, 2018

Final MenuScript Due:
Oct 30, 2018

Publication Date:
Nov 01, 2018
                         Notice Board: Call for PaperVol. 5 Issue 10      Submission Start Date: Oct 01, 2018      Acceptence Notification Start: Oct 10, 2018      Submission End: Oct 15, 2018      Final MenuScript Due: Oct 30, 2018      Publication Date: Nov 01, 2018




Volume IV Issue V

Author Name
Kamlesh Deware, Prof. Madhvi Bhanwar
Year Of Publication
2017
Volume and Issue
Volume 4 Issue 5
Abstract
This paper presents the study and survey analysis on different width size of transistor in CMOS rectifier for output voltage drop. The paper gives information about miniaturizing the CMOS rectifier using two PMOS and NMOS configuration. This investigation focuses on the effect of the width-to-length ratio by using 0.35μm technology. Therefore, increase the width size and minimize the internal resistance. The model is operated at a frequency of 50Hz with an AC voltage source. CADENCE software is used for simulation and designing work
PaperID
2017/IJTRM/5/2017/9051

Author Name
Kapil Jaiswal, Prof. Shivangini Saxena
Year Of Publication
2017
Volume and Issue
Volume 4 Issue 5
Abstract
Industry demands Low-Power and High- Performance devices now-a-days. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thickness. FINFET based SRAM design can be used as an alternative solution to the bulk devices. FINFET is suitable for nano scale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current. As the impact of process variations become increasingly significant in ultra deep submicron technologies, FINFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics.
PaperID
2017/IJTRM/5/2017/9053

Author Name
Khushboo Sisodiya, Vijay Bisen, Jitendra Singh Dodiya
Year Of Publication
2017
Volume and Issue
Volume 4 Issue 5
Abstract
VANET (Vehicular Ad hoc Networks) is an emerging technology. The main application of VANETs are in ITS (Intelligent Transportation System) providing various applications such safety and non-safety related services. VANET is subclass of MANET (Mobile Ad hoc Network). Like MANET, VANET transmit its message to other nodes with the help of multi-hop relaying but dynamic topology change and high speeds of nodes creates a distinction from MANET. The fundamental component for the success of VANET (Vehicular Ad hoc Networks) applications is routing because it handles rapid topology changes and a distributed network efficiently and reliably.
PaperID
2017/IJTRM/5/2017/9055

Author Name
Shraddha Sonone, Asst. Prof. Shiva Bhatnagar
Year Of Publication
2017
Volume and Issue
Volume 4 Issue 5
Abstract
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nano scale. Fin FETs are double-gate devices. The two gates of a FinFET can either be shorted for higher performance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space. This chapter provides an introduction to various interesting Fin FET logic design styles, novel circuit designs, and layout considerations.
PaperID
2017/IJTRM/5/2017/9060